The Xelic Optical Transport Network (OTN) ODTU12 Multiplexer Core (XCO12MX) performs tributary timeslot interleaving of four independent ODU1 data streams and maps them into an ODU2 or OTU2 frame structure. OPU2 multiplex overhead is inserted and automatic justification control is provided based on programmable FIFO thresholds or incoming PJ/PJ2/NJ request signaling. Incoming line side OPU2 overhead is interpreted with error and justification detection reported. System side ODU1 frames are transferred using four independent 16-bit data bus ports operating at a clock rate up to 167.33MHz. Line side data is transferred at an OTU2 rate using a 64-bit data bus operating at 167.33MHz or at an ODU2 rate using a 64-bit data bus operating at 156.83MHz.
The XCO12MX Transmit Processor contains four FIFOs with upper threshold, lower threshold, and overflow/underflow detection. Justifications (positive and negative) for each ODU1 data stream are performed (including both single and double positive justification capability) through a transmit OPU processor. OPU2 overhead insertion includes Payload Structure Identifier (PSI), justification overhead and reserved fields. PSI field insertion consists of payload type, multiplex structure identifier, and reserved bytes multi-frame information. A test mode is available to insert PRBS (PN-11) data into any of the 4 ODU1 frame timeslots. ODU1 frames are mapped into either ODU2 frames or OTU2 frames with blanked FEC. Generated ODU2/OTU2 frames contain blanked OTU2 and ODU2 overhead. FAS and MFAS information is inserted into outgoing frames in addition to OPU2 overhead.
The XCO12MX Receive Processor contains a frame position counter synchronized to incoming FAS and MFAS frame indicators. OPU2 overhead is extracted from incoming frames and interpreted with various error conditions reported to an internal maskable interrupt register. Positive (single and double) and negative justifications are detected and reported though output signaling and internal interrupts. Tributary timeslot deinterleaving is performed on incoming frames and ODU1 frames are de-mapped and delivered to four internal FIFO structures. Configurable depth FIFOs are implemented for the system side ODU1 signal interface.
Performance counters (configurable for interval count capture or latch and clear operation) are provided for the accumulation of inserted (XCO12MX transmit processor) and detected (XCO12MX receive processor) positive and negative justification events. Counters are saturating with latch and clear operation or periodic error sync auto-update mode.
The XCO12MX provides Transmit Processor terminal loopback and Receive Processor facility loopback modes of operation for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.