The Xelic Optical Transport Network (OTN) Time Sliced Flex Multiplexer Core (XCO123TFMX) performs tributary timeslot interleaving and switching of independent time sliced ODU0, ODU1, ODU1e, ODU2, ODU2e, and ODU Flex data streams and maps them into time sliced ODU1, ODU2, and ODU3 frame structures using asynchronous mapping procedure (AMP) or generic mapping procedure (GMP) justification methods. Support is also provided to map incoming ODU3 frames into ODU3+ (overclocked) rate signals. OPU1/OPU2/OPU3 multiplex overhead is inserted and justification control is provided based on incoming request signaling. Incoming
line side OPU1/OPU2/OPU3 overhead is interpreted with error and justification detection reported. Client and line side data is transferred using a time slice identifier and data valid scheme.
The XCO123TFMX Transmit Processor supports time sliced multiplexing for up to two ODU3s, 10 ODU2s, and 40 ODU1s in any legal combination. Incoming ODU0, ODU1, ODU1e, ODU2, ODU2e, and ODU Flex data streams are interleaved and switched to 1.25G or 2.5G timeslots using asynchronous mapping procedure (AMP) or generic mapping procedure (GMP) justification methods. Justification control is provided through incoming request signaling. Payload Structure Identifier (PSI) field insertion is provided and contains payload type (both PT 20 and PT 21 supported), multiplex structure identifier, and reserved bytes multi-frame information. Client ODU3 data signal multiplexing of up to 32 ODU0s, 16 ODU1s, 4 ODU2s, 3 ODU1es (4 ODU1es if overclocking), 3 ODU2es (4 ODU2es if overclocking) and 32/ts ODU Flex signals is supported. Client ODU2 data signal multiplexing of up to 8 ODU0s, 4 ODU1s, or 8/ts ODU Flex signals is also supported along with ODU1 data
signal multiplexing of 2 ODU0s. FAS and MFAS information is inserted into outgoing frames in addition to all OPU overhead fields. FAS and MFAS indicator signaling is also provided at the line side interface. Time sliced bypass operation for requested slices not being multiplexed is also provided.
The XCO123TFMX Receive Processor supports time sliced demultiplexing for up to two ODU3s, 10 ODU2s, and 40 ODU1s in any legal combination. Each ODUk signal being demultiplexed contains a frame position counter
synchronized to incoming FAS and MFAS frame indicator signaling. OPU overhead is extracted from incoming frames and interpreted with various error conditions reported to internal maskable interrupt registers. Positive and negative justifications are detected and reported though output signaling and internal interrupts. Tributary timeslot de-interleaving is performed on incoming ODUk frames. After demultiplexing, a programmable switch allows the routing of ODUk signals to selected client side time sliced interface outputs. Incoming GMP Cm and CnD
information, as well as AMP PJ/NJ information, for each timeslot is provided at the client side interface for client clocking considerations.
Performance counters (configurable for interval count capture or latch and clear operation) are provided for the accumulation of inserted (XCO123TFMX transmit processor) and detected (XCO123TFMX receive processor) positive and negative justification events. Counters are saturating with latch and clear operation or periodic error sync auto-update mode.
The XCO123TFMX provides Transmit Processor terminal loopback and Receive Processor facility loopback modes of operation for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCO123TFMX core available under flexible single use licensing terms with netlist or source code deliverables.
- Implements flexible data bus architecture.
- Implements 16-bit register interface for programming of internal registers.
- Complies with ITU-T G. 709 and ITU-T G. 798 specifications.
- Provides transmit and receive loopback options for diagnostic purposes.
- Supports multiplexing of up to two ODU3s, 10 ODU2s, and 40 ODU1s in any legal combination.
- Incoming time sliced ODUk data streams are interleaved and switched to 1.25G or 2.5G timeslots using asynchronous mapping procedure (AMP or generic mapping procedure (GMP) justification methods.
- Flexible OPU overhead field insertion is provided with PT 20 and PT 21 support.
- Provides justification through incoming request signaling.
- Inserts FAS/MFAS framing information with output signaling provided.
- Programmable positive and negative justification counters provided with user defined interval or errored second accumulation.
- Performs OPU tributary 1.25G and 2.5G timeslot deinterleaving and de-mapping into ODUk frames.
- Supports both AMP and GMP justification methods.
- Provides configurable FIFOs for ODUk data streams.
- Contains frame position counter synchronized to incoming FAS/MFAS signaling.
- Provides saturating counters for positive, double positive, negative, and double negative justifications detected with programmable latch and clear or incoming error sync capture configurations.
- Interprets and extracts incoming OPU overhead information and reports errors to internal register with maskable interrupt capability.