4Kx16 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
Parallel FLASH Memory Controller
Features a fully synchronous command interface and a set of configurable timing parameters for compatibility with different devices.
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Block Diagram of the Parallel FLASH Memory Controller IP Core
![Parallel FLASH Memory Controller Block Diagam](http://www.design-reuse.com/sip/blockdiagram/36194/20150321053716-main-flash_cont_block_diag.png)