Hardent's ECC/FEC (Error-Correcting Code/Forward Error Correction) proprietary tool suite implements Reed-Solomon algorithms with a high-performance parallel architecture.
Hardent uses the tool suite, combined with its expertise in ASIC/FPGA and system design, to customize the design of the hardware ECC/FEC decoder IP core to each customer’s unique requirements and target application.
The tool suite implements the ECC/FEC encoder function using user-defined parameters, including the level of parallelization (symbol per clock) of the circuit, in order to allow for optimization of data throughput and/or gate count.
- User-configurable FEC parameters
- Bits per symbol (m)
- Codeword length (n), message length (k)
- Number of parity symbols (2t)
- Primitive polynomial and generator polynomial
- Configurable parallelization level (symbols per clock cycle)
- Error and erasure decoding
- Performance and statistic counters
- Fully synchronous design
- Hardent’s IP portfolio offers customers ready-made solutions to accelerate product development and meet demanding time-to-market schedules.
- Developed by our team of experienced FPGA and ASIC designers, our IP products have undergone extensive verification and offer proven interoperability and compatibility
- Encrypted RTL source code IP core
- Functional and structural coverage reports
- Comprehensive integration guide
- Technical support and maintenance updates
- Optical links
- High-speed electrical links
- Fault-tolerant SSD storage
- Deep space transmission and telemetry
Block Diagram of the Parallel Reed-Solomon ECC/FEC RX Custom IP Core