Parallel Reed-Solomon ECC/FEC TX Custom IP Core
Hardent uses the tool suite, combined with its expertise in ASIC/FPGA and system design, to customize the design of the hardware ECC/FEC encoder IP core to each customer’s unique requirements and target application.
The tool suite implements the ECC/FEC encoder function using user-defined parameters, including the level of parallelization (symbol per clock) of the circuit, in order to allow for optimization of data throughput and/or gate count.
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Block Diagram of the Parallel Reed-Solomon ECC/FEC TX Custom IP Core
