English
You are here:
Parallel Reed-Solomon ECC/FEC TX Custom IP Core
Hardent's ECC/FEC (Error-Correcting Code/Forward Error Correction) proprietary tool suite implements Reed-Solomon algorithms with a high-performance parallel architecture.
Hardent uses the tool suite, combined with its expertise in ASIC/FPGA and system design, to customize the design of the hardware ECC/FEC encoder IP core to each customer’s unique requirements and target application.
The tool suite implements the ECC/FEC encoder function using user-defined parameters, including the level of parallelization (symbol per clock) of the circuit, in order to allow for optimization of data throughput and/or gate count.
Hardent uses the tool suite, combined with its expertise in ASIC/FPGA and system design, to customize the design of the hardware ECC/FEC encoder IP core to each customer’s unique requirements and target application.
The tool suite implements the ECC/FEC encoder function using user-defined parameters, including the level of parallelization (symbol per clock) of the circuit, in order to allow for optimization of data throughput and/or gate count.
View Parallel Reed-Solomon ECC/FEC TX Custom IP Core full description to...
- see the entire Parallel Reed-Solomon ECC/FEC TX Custom IP Core datasheet
- get in contact with Parallel Reed-Solomon ECC/FEC TX Custom IP Core Supplier
Block Diagram of the Parallel Reed-Solomon ECC/FEC TX Custom IP Core
