The Partial Reconfiguration (PR) Bitstream Monitor can be used to identify partial bitstreams as they flow through the design. This information can be used for debugging or to help manage system applications such as blocking bitstream loads. Identifiers embedded at key places in partial bitstreams are extracted are reported by the core. This information can be passed to Vivado HW Debugger using an ILA core to work out what partial bitstream was fetched, if it was fetched in its entirety, and how far through the datapath it went.
- ICAP, AXI4MM (partial support), AXI4-Lite and Generic datapaths supported
- Partial Bitstreams can be traced in the Configuration Engine
- Live and buffered status
- Optional Signal based or AXI4-Lite control
- Optional AXI4-Lite status (signal status is always available)