The Partial Reconfiguration Controller (PRC) IP provides management functions for Partial Reconfiguration designs. When hardware or software trigger events occur, the PRC pulls partial bitstreams from memory and delivers them to an internal configuration access port (ICAP). The PRC also assists with logical decoupling and startup events, customizable per Reconfigurable Partition.
This core is intended for enclosed systems where all of the Reconfigurable Modules are known to the controller. The optional AXI4-Lite register interface allows the core to be reconfigured at run time, so it can also be used in systems where the Reconfigurable Modules can change in a deployed system. The core can be customized for number of Virtual Sockets, number of Reconfigurable Modules per Virtual Sockets, operation and interface.