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4K x 8 Bits OTP (One-Time Programmable) IP, GF22nm FDX 0.8V/1.8
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PCI Compiler, 32-bit Master/Target
Altera's PCI Compiler provides a complete, easy-to-use solution for implementing a PCI interface with Altera devices. The PCI Compiler contains the Altera pci_mt32 and pci_t32 MegaCore functions and supports the MegaWizard® Plug-In Manager design flow.
Altera?s PCI MegaCore functions are fully tested to meet the requirements of the PCI-SIG PCI Local Bus Specification, Revision 3.0 and Compliance Checklist, Revision 3.0. You can test drive Altera PCI MegaCore functions using the OpenCore Plus feature to compile, simulate, and hardware-test the functions within your custom logic. When you are ready to license a function, contact your local Altera sales representative.
The pci_mt32 and pci_t32 MegaCore functions provide fully compliant, 32 bit, 66 MHz PCI bus interface support. The pci_mt32 and pci_t32 cores are optimized for the Stratix® FPGA series, Arria® GX FPGA series, Cyclone® FPGA series, and the HardCopy® ASICs series. Additionally, the pci_mt32 and pci_t32 cores are optimized for MAX® II CPLDs.
Altera?s PCI MegaCore functions are fully tested to meet the requirements of the PCI-SIG PCI Local Bus Specification, Revision 3.0 and Compliance Checklist, Revision 3.0. You can test drive Altera PCI MegaCore functions using the OpenCore Plus feature to compile, simulate, and hardware-test the functions within your custom logic. When you are ready to license a function, contact your local Altera sales representative.
The pci_mt32 and pci_t32 MegaCore functions provide fully compliant, 32 bit, 66 MHz PCI bus interface support. The pci_mt32 and pci_t32 cores are optimized for the Stratix® FPGA series, Arria® GX FPGA series, Cyclone® FPGA series, and the HardCopy® ASICs series. Additionally, the pci_mt32 and pci_t32 cores are optimized for MAX® II CPLDs.
Features
- Contains 32 bit PCI master/target and 32 bit PCI target functionsÂ
- Fully compliant with the timing and functional requirements of the PCI Special Interest Group (PCI-SIG®) PCI Local Bus Specification, Revision 3.0Â
- Extensively tested in hardware
- Intellectual property (IP) functional simulation models provide cycle-accurate behavioral simulations in industry-standard Verilog HDL and VHDL simulation tools
- Open-source PCI testbench provides flexible PCI bus functional models to verify Altera® PCI MegaCore function-based applications in industry-standard Verilog HDL and VHDL simulation tools
- Reference designs for popular functionality implemented on the local side of the PCI MegaCore functions, including direct memory access (DMA) engines, datapath FIFO architectures, and SDRAM interfaces
Benefits
- SOPC Builder Ready: No
- Qsys Compliant: No
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PCI IP
- PCI Express (PCIe) Gen4 x4
- PCI Express (PCIe) Gen4 x8
- Complete PCIe 4.0 Soft IP supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, AER and more
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- PCIe 5.0 Controller
- XpressCCIX-AXI Controller IP for PCIe 5.0 with CCIX ESM support