The PCI Express 2.0 PHY IP Core in UMC 28HPC is a high-speed, high-performance, and low power IP core that is fully compliant to the PCI Express Specification 1.1 and 2.0. The IP core is designed for applications in computing, networking, storage, servers, wireless, and consumer electronics.
The PCIe2.0 PHY IP is a complete physical layer (PHY) IP solution designed for mobile and consumer applications. Compliant with the PCIe2.0 base specifications, the PHY IP integrates mixed-signal circuits to support both 2.5GT/s and 5.0GT/s data transmission rates. The PCIe2.0 PHY IP consists of both the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), and connects easily to either the PCIe2.0 MAC layer using the standard PIPE-3.0 interface. The feature-rich IP core is highly configurable that allows a target design to be implemented with the least number of gates and highest performance.