Tunable SM4 (ECB, CBC, CTR, XTS, CCM, GCM) accelerator - optional SCA protection
PCI Express 2.0 PHY IP Core(Silicon Proven in UMC 28HPC)
The PCIe2.0 PHY IP is a complete physical layer (PHY) IP solution designed for mobile and consumer applications. Compliant with the PCIe2.0 base specifications, the PHY IP integrates mixed-signal circuits to support both 2.5GT/s and 5.0GT/s data transmission rates. The PCIe2.0 PHY IP consists of both the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), and connects easily to either the PCIe2.0 MAC layer using the standard PIPE-3.0 interface. The feature-rich IP core is highly configurable that allows a target design to be implemented with the least number of gates and highest performance.
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pcie3.0ip IP
- PCIe 5.0 Controller IP supporting Root Complex, End Point, Switch Port compliant with PCIe 5.0/4.0/3.0/2.0/1.0 and fully synthesizable
- PCIe 3.0 PHY IP with 8GT/s optimized for low power consumption (Silicon Proven in TSMC 28HPC+)
- PCIe 4.0 SerDes PHY IP (Silicon Proven in UMC 28HPC)
- Quad Lane 5Gbps PCIe 2.0 PHY IP (Silicon Proven in TSMC 22ULP/ULL)
- 5G PHY IP for PCIe 2.0 (Silicon Proven in TSMC 55ULP / 65ULP)
- PCIe Gen2 PHY IP (Silicon Proven in SMIC 40LL)