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PCI Express 5.0/4.0/3.0/2.1/1.1 Core
The Northwest Logic Expresso 5.0 Core is part of Rambus' PCI Express Solution. This solution is designed to achieve maximum PCI Express throughput while being easy to use.
The Expresso 5.0 Core separately, or in combination with
Rambus family of DMA Cores and DMA Drivers, provide
the maximum system throughput on a PCI Express link.
The core is specifically designed for ease of use including full
receive packet decoding, complete error handling, automatic
handling of PCI Express message packets and comprehensive
system-debug and link monitoring support.
The core is delivered integrated and verified with the user’s
Target PHY. Contact Rambus for a complete list of
supported PHYs. To accelerate simulations, the core is also
delivered integrated with a fast-simulating behavioral PHY.
The core is provided with the Expresso Testbench which provides a PCI Express Bus Functional Model.
The core is compliant with the current version of the PCI Ex- press Base Specification 5.0.
The core has been extensively validated with the Avery Design Systems PCI-Xactor PCI Express Compliance Suite and Northwest Logic Expresso Testbench.
Rambus also provides IP Core customization services. Contact Rambus for a quote.
The Expresso 5.0 Core separately, or in combination with
Rambus family of DMA Cores and DMA Drivers, provide
the maximum system throughput on a PCI Express link.
The core is specifically designed for ease of use including full
receive packet decoding, complete error handling, automatic
handling of PCI Express message packets and comprehensive
system-debug and link monitoring support.
The core is delivered integrated and verified with the user’s
Target PHY. Contact Rambus for a complete list of
supported PHYs. To accelerate simulations, the core is also
delivered integrated with a fast-simulating behavioral PHY.
The core is provided with the Expresso Testbench which provides a PCI Express Bus Functional Model.
The core is compliant with the current version of the PCI Ex- press Base Specification 5.0.
The core has been extensively validated with the Avery Design Systems PCI-Xactor PCI Express Compliance Suite and Northwest Logic Expresso Testbench.
Rambus also provides IP Core customization services. Contact Rambus for a quote.
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PCIe 5.0 Controller IP
- PCIe 5.0 Controller
- XpressCCIX-AXI Controller IP for PCIe 5.0 with CCIX ESM support
- PCIe 5.0 PHY IP with 32GT/s optimized for low power consumption (Silicon Proven in TSMC 12FFC)
- PCIe 5.0 SerDes PHY
- Gen5 PCIe Hybrid Controller with SR-IOV and ARI Support
- Configurable controllers for PCIe 5.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications