PCI Express Gen 1/Gen 2 Phy
Each transmit section of the TRC5024CPA contains a low-jitter clock synthesizer, a parallel to serial converter with built in PCS transmit functions, and a CMOS output driver with selectable de-emphasis for use in backplane applications.
Each receive section contains an input limiting amplifier with on-chip terminations and selectable equalization levels, clock/data recovery PLL, and PCS receive functions. Built-in serial and parallel loopback modes. PRBS generator/checker and error detectors aid in support of testing.
The TRC5024CPA requires no external components for its clock synthesizers and clock recovery PLL. Three external resistors are needed to set the proper bias currents for its onchip terminations.
TRC5024CPA has low jitter generation and high jitter tolerance making it ideal for integration in SoCs and ASICs in the presence of multiple clocks and noise. TSMC is available in TSMC 65 nm G process and can be ported to other processes.
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Block Diagram of the PCI Express Gen 1/Gen 2 Phy IP Core

PCI Express Phy IP
- Controller IP for PCIe 2.1 as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification
- Controller IP for PCIe 1.1 as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification
- PCI Express 5.0/4.0/3.0/2.1/1.1 Core from Rambus
- Complete PCIe 4.0 Soft IP supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, AER and more
- Configurable PCI Express 2.1 Supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Gen5 PCIe Hybrid Controller with SR-IOV and ARI Support