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PCI Express Gen 4 PHY
Features
- Support 16GT 8GT 5GT 2.5GT data rate
- Compliant with PCI Express 4.0, 3.1, 2.1, 1.1 and PIPE 4.2 standards
- x1, x2, x4, x8, x16 lane configuration with bifurcation
- Multi-tap adaptive programmable continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE)
- Support L1 SUB low power consumption mode status
- Support SRIS
- Built-in self-check vector, PRBS generation and check mechanism
- Temperature range -40℃-125℃
- Support Flip chip packaging
View PCI Express Gen 4 PHY full description to...
- see the entire PCI Express Gen 4 PHY datasheet
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PCIE PHY IP
- PCIe 5.0 PHY in TSMC (16nm)
- 32G Multi Rate SerDes PHY - GlobalFoundries 22FDX
- PCIe 6.0 SerDes PHY
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- 32G Multi-protocol SerDes PHY
- PCIe 4.0 PHY in GlobalFoundries (14nm)