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PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 55nm SP process
PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process.
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PCIe PHY IP
- PCIe 5.0 PHY in TSMC (16nm)
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 4.0 PHY in GlobalFoundries (14nm)
- PCIe 4.0 PHY in Samsung (14nm)
- PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, 7nm)
- 32G Multi Rate SerDes PHY - GlobalFoundries 22FDX