Application-optimized, high-performance controller IP for PCIe
The Cadence® Controller IP for PCIe 4.0 provides the logic required to integrate a root complex (RC), endpoint (EP), or dual mode (DM) controller into any system-on-chip (SoC). Compliant with PCIe 4.0, 3.1, 2.1, and 1.1 specifications, the Controller IP has over 100 configuration features to customize the controller to the specific needs of any computing, networking, or storage application. The Controller IP is engineered to quickly and easily integrate into any SoC and connect seamlessly to a Cadence or third-party PIPE 4.0-compliant PHY. Client applications access the controller through an industry-standard Arm® AMBA® interface or through a native Cadence interface, Host Adaptation Layer (HAL). The Controller IP has been extensively tested using Cadence Verification IP for PCIe as well as the Cadence Palladium® series verification computing platform. Cadence offers a comprehensive IP solution that is in volume production and successfully implemented in dozens of applications.