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PCI Express (PCIe) Gen3 x8
The Controller IP for PCIe 3.0 has over 100 configuration features, and 1500+ input parameters, to customize the controller to the specific needs of any application. With rich configurations and product features, the PCIe 3.0 controller is architected to quickly and easily integrate into any SoC, and connect seamlessly to a Cadence, or third-party, PIPE 3.0- or PIPE 4.2-compliant PHY. With consumers need for mobile devices capable of providing enough processing power to perform tasks like making payments, playing and streaming HD videos and playing demanding video games, the Controller is a high performance solution, benchmarked at 95% of theoretical maximum throughput.
Features
- Compliant with PCIe 3.0, 2.1, and 1.1 specifications
- Configurable as root complex, endpoint, or dual mode devices
- Ultra-low transmit/receive latency and high bandwidth
- Supports x1, x2, x4, x8, and x16 configurations
- Single root I/O virtualization (SR-IOV) and bifurcation options
- 16 or 32-bit PIPE 3.0 or PIPE 4.2 interface
Benefits
- Low-risk solutions - silicon-proven design
- Ease-of-use - customizable with easy integration
- High performance - benchmarked at 95% of theoretical maximum throughput
Deliverables
- Clean, readable, synthesizable RTL Verilog file
- Verification testbench example with integrated stimulus and monitors
- Verification test-plan and reports
- Comprehensive user guide
- Register descriptions
- Synthesis and STA scripts
View PCI Express (PCIe) Gen3 x8 full description to...
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PCIe IP
- PCIe 5.0 PHY in TSMC (16nm)
- Complete PCIe 4.0 Soft IP supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, AER and more
- Customizable Embedded Multi-port PCIe Switch
- PCIe 5.0 Controller
- XpressCCIX-AXI Controller IP for PCIe 5.0 with CCIX ESM support
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications