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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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PCI Express (PCIe) Gen4 x16
Controller IP for PCIe 4.0 - high performance, silicon-proven IP, configured to your specific needs.
The cloud computing revolution, combined with tons of smartphone applications and Internet of Things (IoT products) is taking a toll on data traffic, also driving change in datacenter device architecture. High speed communication within and between servers and storage are necessary to support video, and the growth of dataset and associated analytics.
The Cadence Design IP for PCI Express 4.0 provides the logic required to integrate a root complex (RC), endpoint (EP), or dual mode (DM) controller into any system-on-chip (SoC), thus resolving the need for PCIe 4.0 support conforming to PCI Express 4.0 (v.0.7), 3.0, 2.1 and 1.1. The Cadence Design IP for PCIe 4.0 can be configured for up to 16 lanes bandwidths at the Physical Layer.
Client applications access the controller through industry standard ARM, AMBA AXI3 or AXI interface or through the native host adaptation layer (HAL) interface.
The superior architecture allows the PCIe controller to achieve near theoretical throughput rates. Pre-configured controller cores are available to provide customers with off-the-shelf IP pre-designed specifically for consumer, enterprise, and mobile applications.
The cloud computing revolution, combined with tons of smartphone applications and Internet of Things (IoT products) is taking a toll on data traffic, also driving change in datacenter device architecture. High speed communication within and between servers and storage are necessary to support video, and the growth of dataset and associated analytics.
The Cadence Design IP for PCI Express 4.0 provides the logic required to integrate a root complex (RC), endpoint (EP), or dual mode (DM) controller into any system-on-chip (SoC), thus resolving the need for PCIe 4.0 support conforming to PCI Express 4.0 (v.0.7), 3.0, 2.1 and 1.1. The Cadence Design IP for PCIe 4.0 can be configured for up to 16 lanes bandwidths at the Physical Layer.
Client applications access the controller through industry standard ARM, AMBA AXI3 or AXI interface or through the native host adaptation layer (HAL) interface.
The superior architecture allows the PCIe controller to achieve near theoretical throughput rates. Pre-configured controller cores are available to provide customers with off-the-shelf IP pre-designed specifically for consumer, enterprise, and mobile applications.
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