English
You are here:
PCI Express (PCIe) Gen4 x16
Controller IP for PCIe 4.0 - high performance, silicon-proven IP, configured to your specific needs.
The cloud computing revolution, combined with tons of smartphone applications and Internet of Things (IoT products) is taking a toll on data traffic, also driving change in datacenter device architecture. High speed communication within and between servers and storage are necessary to support video, and the growth of dataset and associated analytics.
The Cadence Design IP for PCI Express 4.0 provides the logic required to integrate a root complex (RC), endpoint (EP), or dual mode (DM) controller into any system-on-chip (SoC), thus resolving the need for PCIe 4.0 support conforming to PCI Express 4.0 (v.0.7), 3.0, 2.1 and 1.1. The Cadence Design IP for PCIe 4.0 can be configured for up to 16 lanes bandwidths at the Physical Layer.
Client applications access the controller through industry standard ARM, AMBA AXI3 or AXI interface or through the native host adaptation layer (HAL) interface.
The superior architecture allows the PCIe controller to achieve near theoretical throughput rates. Pre-configured controller cores are available to provide customers with off-the-shelf IP pre-designed specifically for consumer, enterprise, and mobile applications.
The cloud computing revolution, combined with tons of smartphone applications and Internet of Things (IoT products) is taking a toll on data traffic, also driving change in datacenter device architecture. High speed communication within and between servers and storage are necessary to support video, and the growth of dataset and associated analytics.
The Cadence Design IP for PCI Express 4.0 provides the logic required to integrate a root complex (RC), endpoint (EP), or dual mode (DM) controller into any system-on-chip (SoC), thus resolving the need for PCIe 4.0 support conforming to PCI Express 4.0 (v.0.7), 3.0, 2.1 and 1.1. The Cadence Design IP for PCIe 4.0 can be configured for up to 16 lanes bandwidths at the Physical Layer.
Client applications access the controller through industry standard ARM, AMBA AXI3 or AXI interface or through the native host adaptation layer (HAL) interface.
The superior architecture allows the PCIe controller to achieve near theoretical throughput rates. Pre-configured controller cores are available to provide customers with off-the-shelf IP pre-designed specifically for consumer, enterprise, and mobile applications.
Features
- Compliant with PCIe 4.0 (v0.7), 3.0, 2.1, and 1.1 specifications
- 500MHz or 1GHz core operation
- Configurable as root complex, endpoint, or dual mode devices
- Ultra-low transmit/receive latency and high bandwidth
- SR-IOV and multifurcation options
- Support for up to 4K payload size and 256 functions
- ECNs, Error Counters, ECRC, and end-to-end datapath parity support
Benefits
- Enables high bandwidth for short and long reach applications
- Superscalar design for high performance, low latency, and high throughput
- Configured to your specific needs – efficient implementation results in minimal gate count
- Optimized for use with Cadence Multi-link PHY
Deliverables
- Clean, readable, synthesizable RTL Verilog file
- Verification testbench example with integrated stimulus and monitors
- Verification test-plan and reports
- Comprehensive user guide
- Register descriptions
- Synthesis and STA scripts
View PCI Express (PCIe) Gen4 x16 full description to...
- see the entire PCI Express (PCIe) Gen4 x16 datasheet
- get in contact with PCI Express (PCIe) Gen4 x16 Supplier
PCIe
- PCIe 3.0 PHY IP TSMC 28HPM
- PCIe 3.0 PHY IP TSMC 28HPC
- PCI Express (PCIe) Gen4 x4
- PCI Express (PCIe) Gen4 x8
- Complete PCIe 4.0 Soft IP supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, AER and more
- PCIe 5.0 Controller