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Low latency Network TAP IP-Core for full duplex 100M/1G Ethernet links
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PCI Express (PCIe) Gen4 x8
Cadence Controller IP for PCIe 4.0 is engineered to quickly and easily integrate into any SoC and connect seamlessly to a Cadence or 3rd-party PIPE 4.0-compliant PHY. The PCIe 4.0 Controller provides provides the logic required to integrate a root complex (RC), endpoint (EP), or dual mode (DM) controller into any system-on-chip (SoC). The PCIe 4 Controller is designed for increasing data traffic and changes in datacenter device architecture. The PCIe 4.0 Controller is compliant with PCIe 4.0 (r0.7), PCIe 3.0, PCIe 2.1 and PCIe 1.1 specifications. The PCIe 4.0 Controller has over 100 configuration features to customize the controller to the specific needs of any computing, networking or storage application.
Features
- Compliant with PCIe 4.0 (v0.7), 3.0, 2.1, and 1.1 specifications
- 500MHz or 1GHz core operation
- Configurable as root complex, endpoint, or dual mode devices
- Ultra-low transmit/receive latency and high bandwidth
- SR-IOV and multifurcation options
- Support for up to 4K payload size and 256 functions
- ECNs, Error Counters, ECRC, and end-to-end datapath parity support
Benefits
- Enables high bandwidth for short and long reach applications
- Superscalar design for high performance, low latency, and high throughput
- Configured to your specific needs – efficient implementation results in minimal gate count
- Optimized for use with Cadence Multi-link PHY
Deliverables
- Clean, readable, synthesizable RTL Verilog file
- Verification testbench example with integrated stimulus and monitors
- Verification test-plan and reports
- Comprehensive user guide
- Register descriptions
- Synthesis and STA scripts
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