PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
SMS5000 does not require any external Loop filter capacitor(s) for clock Synthesis PLL or Clock recovery circuitry making it immune to PCB related noise typically encountered, and provides a completely integrated solution.
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Block Diagram of the PCI Express PHY serial link PIPE Transceiver IP cell/hard macro

PCI-Express PIPE PHY Transceiver IP
- 1-64Gbps PCI-Express Gen1 - Gen6 PHY and CXL SerDes
- USB 3.1 PHY IP ((10G/5G),Silicon proven in TSMC 28HPC+)
- PCIe 5.0 PHY in TSMC (16nm)
- USB 3.1 PHY IP ((10G/5G),Silicon proven in UMC 28HPC+)
- USB 3.1 PHY IP ((10G/5G),Silicon proven in SMIC 14SF+/ SF++)
- USB 3.2 PHY IP ((20G/10G),Silicon proven in UMC 28HPC+)