PCI Express is a high performance, fully scalable, well defined standard for a wide variety of computing and communications platforms. It has been defined to provide software compatibility with existing PCI drivers and operating systems. Being a packet based serial technology, PCI Express greatly reduces the number of required pins and simplifies board routing and manufacturing. PCI Express is a point-to-point technology, as opposed to the multidrop bus in PCI. Each PCI Express device has the advantage of full duplex communication with its neighbor to greatly increase overall system bandwidth. The basic data rate for a single lane is double that of the 32 bit/33 MHz PCI bus. A four lane link has eight times the data rate in each direction of a conventional bus.
Lattice’s PCI Express Root Complex (RC) Lite core provides an x1 or x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCI express protocol stack. This IP is a lighter version of the root complex intended to use in simple bridging application to local bus. This solution supports the high value, low power LatticeECP3 and LatticeECP2M FPGA device families.
* Download demo bitstream from the PCI Express Demo page.
* Visit the PCI Express Solutions page for other demos, boards and development kits.
- Download demo bitstream from the PCI Express Demo page.
- Visit the PCI Express Solutions page for other demos, boards and development kits.
Block Diagram of the PCI Express x1, x4 Root Complex Lite IP Core