PCI-X is an evolutionary design and an enhancement of the industry standard PCI-X bus. The PCI-X enables 64-bit designs to operate at speeds upto 133 MHz. The PCI-X achieves this performance by implementing a register-to-register protocol and improved transaction processing called split transactions. This feature enables multi-threading split transactions. The SS V6201 PCI-X Megacell can be used with both legacy PCI-2.2 systems as well as with the newer PCI-X systems.
- Supports bus operation up to 133 Mhz and Dynamically handles 64-bit and 32-bit data operations.
- Supports split transactions and all PCI-X/PCI-2.2 commands
- Parameterized PCI-X AD bus width and implementation of several PCI-2.2 optional features
- Access to SS V6201 configuration space by application (optional on user request)
- Parameterized configuration space implementation
- Fully synchronous design and Available in Verilog source code
- Supports simultaneous PCI-X and application bus operation and PCI-X initiator and target operation
- Zero-wait-state PCI-X burst transactions
- Automatic handling of PCI-X bus activities such as retries, disconnects, and latency time outs that they are transparent to the user application.
- Partitioned along functional boundaries for best timing performance
- Includes a separate I/O pad module to be used for instantiating technology specific I/O pads.
- SoC Integration
- Fully synthesizable Verilog RTL source code
- Documentation - Data Sheet, User Guide, Verification Description Document
- Self checking Verification Suite
- Synthesis and STA Scripts