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PCIe 2.0 End Point IP Core - PCIe with FIFO Interface
The Arasan PCI Express End Point is a high-speed, high-performance, and lowpowerIP core that is fully compliant to the PCI Express Specification 1.1 and 2.0. The IP core is designed for applications in computing, networking, storage, servers, wireless, and consumer electronics. The feature-rich IP core is highly configurable that allows a target design to be implemented with the least number of gates and highest performance.
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Block Diagram of the PCIe 2.0 End Point IP Core - PCIe with FIFO Interface
PCI PCI Express IP
- PCI Express 4.0/3.0/2.1/1.1 Support from Rambus
- PCIe 5.0 Controller
- Configurable PCI Express 2.1 Supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Controller IP for PCIe 2.1 as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification
- Configurable PCI Express 1.1 Supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Gen5 PCIe Hybrid Controller with SR-IOV and ARI Support