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PCIe 2.0 End Point IP Core - PCIe with FIFO Interface
The Arasan PCI Express End Point is a high-speed, high-performance, and lowpowerIP core that is fully compliant to the PCI Express Specification 1.1 and 2.0. The IP core is designed for applications in computing, networking, storage, servers, wireless, and consumer electronics. The feature-rich IP core is highly configurable that allows a target design to be implemented with the least number of gates and highest performance.
Features
- PCI Express Specification Rev 1.1 and Rev2.0
- PIPE Specification Rev 1.87
- 8-bit/16-bit PIPE interface
- x1, x2, and x4 lanes
- ASPM and software controlled power management
- Legacy PCI, and MSI/MSI-X interrupts support
- AHB master/slave with FIFO interface
- Optional 8051 host interface
- Optional custom bus interface
Benefits
- Fully compliant core
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
- Unencrypted source code allows easy implementation
- Customer training available
- Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglass
Deliverables
- RMM Compliant Synthesizable RTL design in Verilog
- Easy-to-use test environment
- Synthesis scripts
- Technical documents
- Sample device drivers
Block Diagram of the PCIe 2.0 End Point IP Core - PCIe with FIFO Interface
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PCI PCI Express
- PCI Express (PCIe) Gen4 x4
- PCI Express (PCIe) Gen4 x8
- PCI Express (PCIe) Gen4 x16
- Complete PCIe 4.0 Soft IP supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, AER and more
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- PCIe 5.0 Controller