The Peripheral Component Interconnect PHY IP for PCI Express® 2.1 includes’ high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today’s PCI Express (PCIe®) designs while being extremely low in power and area.
The PCIe2.0 PHY IP consists of both the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), and connects easily to either the PCIe2.0 MAC layer using the standard PIPE-3.0 interface.
The PCIe2.0 PHY IP transceiver is optimized for low power consumption.
The PCIe2.0 PHY IP comprises a complete on-chip physical transceiver solution with Electro Static Discharge (ESD) protection, built-in self test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for high-performance designs