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PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 14SF+
The PCIe 2.0 transceiver IP supports all PCIe 2.0 Base applications. It complies with the PIPE 3.0 standard. This IP incorporates high-speed mixed signal circuits to handle PCIe 2.0 traffic at 5Gbps and is backward compatible with PCIe 1.0 data speeds at 2.5Gbps. It is designed to consume less power and have a small die area. The PCIe 2.0 IP may address the needs for diverse channel circumstances by supporting both TX and RX equalization algorithms.
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Block Diagram of the PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 14SF+
PCIe 2.0 IP Cores IP
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Configurable controllers for PCIe 2.0/1.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
- USB 3.0 SATA 3.0 PCIe 2.0 XAUI MultiPHY
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe Gen2 PHY
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP