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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
A wide variety of PCIe 2.0 Base applications are available with PCIe 2.0 transceiver IP. It adheres to the PIPE 3.0 standard. In order to enable PCIe 2.0 traffic at 5Gbps and be backward compatible with PCIe 1.0 data rate at 2.5Gbps, this IP includes highspeed mixed signal circuits. It is designed to consume less power and have a small die area. The PCIe 2.0 IP may satisfy the needs for various channel circumstances since it supports both TX and RX equalization approaches.
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Block Diagram of the PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
