English
You are here:
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 55ULP/65ULP
The PCIe2.0 PHY IP is a complete physical layer (PHY) IP solution designed for mobile and consumer applications. Compliant with the PCIe2.0 base specifications, the PHY IP integrates mixed-signal circuits to support both 2.5GT/s and 5.0GT/s data transmission rates. The PCIe2.0 PHY IP consists of both the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), and connects easily to either the PCIe2.0 MAC layer using the standard PIPE-3.0 interface.
The PCIe2.0 PHY IP transceiver is optimized for low power consumption and minimal die area (sub-0.30mm2), without sacrificing performance and high-data throughput. The PCIe2.0 PHY IP comprises a complete on-chip physical transceiver solution with Electro Static Discharge (ESD) protection, built-in self test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for high-performance designs.
The PCIe2.0 PHY IP transceiver is optimized for low power consumption and minimal die area (sub-0.30mm2), without sacrificing performance and high-data throughput. The PCIe2.0 PHY IP comprises a complete on-chip physical transceiver solution with Electro Static Discharge (ESD) protection, built-in self test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for high-performance designs.
View PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 55ULP/65ULP full description to...
- see the entire PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 55ULP/65ULP datasheet
- get in contact with PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 55ULP/65ULP Supplier
Block Diagram of the PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 55ULP/65ULP
