PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 7nm
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Block Diagram of the PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 7nm
PCIe 2.0 IP Cores IP
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Compute Express Link (CXL) 1.1/2.0/3.0 Controller
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- CXL 2.0 Agilex FPGA Acclerator Card
- PCIe 2.0 PHY in Fujitsu (40nm)
- PCIe 2.0 PHY in SMIC (40nm, 28nm)