English
You are here:
PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
Rambus PCIe 2.1 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 Controller is compliant with the PCI Express 2.1 specification, as well as with the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including data path size, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power. Rambus PCIe 2.1 Controller is the #1 choice for designers requiring enterprise-class features, highest performance, reliability, and scalability.
View PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support full description to...
- see the entire PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support datasheet
- get in contact with PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support Supplier
PCIe IP
- PCIe Controller Testbench
- PCIe 5.0 PHY in TSMC (16nm)
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect