PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
PCI Express 3.0, 2.0, 1.1 Controller IP Core - Configurable
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Block Diagram of the PCI Express 3.0, 2.0, 1.1 Controller IP Core - Configurable
PCI Express Controller IP
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe Controller Testbench
- PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface