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MIPI C-PHY/D-PHY Combo Universal IP, 4.5Gsps/4.5Gbps in TSMC 22ULP
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PCI Express 3.0, 2.0, 1.1 Controller IP Core - Configurable
Rambus PCIe 3.0 Controller is a highly configurable PCIe 3.0 interface Soft IP designed for ASIC and FPGA implementations supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, Advanced Error Reporting (AER) and more. Rambus PCIe 3.0 Controller is the industry’s PCIe IP of choice for enterprise-class applications requiring the highest performance, reliability, and flexibility.
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Block Diagram of the PCI Express 3.0, 2.0, 1.1 Controller IP Core - Configurable
PCI Express Controller IP
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- Universal NVM Express Controller (UNEX)
- PCIe Controller Testbench