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PCIe 3.0/3.1/USB3.0/SATA3 Combo PHY TSMC 22ULP/ULL
The Innosilicon PCIE3.0 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface for PCIE3.0 Super-Speed standard from Intel. The PHY supports PCIE3.0(8Gb/s/5Gb/s/2.5Gb/s) physical layer specifications.
The PHY module includes a top level wrapper integrating both the Physical Media Attachment (PMA) layer, and the Physical Coding Sub-Block (PCS) layer.
The PHY module includes a top level wrapper integrating both the Physical Media Attachment (PMA) layer, and the Physical Coding Sub-Block (PCS) layer.
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PCIe3.0 IP
- Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 28HPC process
- Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process
- Single Lane and Quad Lane 8Gbps PCIe3.0 PHY in Samsung 28LPP process
- Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 65G process
- USB 3.0 PCIe 3.0 SATA 3.0 Combo PHY IP, Silicon proven in SMIC 14SF+/SF++
- USB 3.2 PCIe 3.1 SATA 3.2 Combo PHY IP, Silicon proven in UMC 28HPC+