T2M offers best in class highly configurable PCIe 3.0 PHY, targeted for both enterprise and client application, complaint to PCie 3.0 specification and ECN 1.0a. The PHY IP is designed to support a wide range of applications and can provides maximum throughput through its eight lanes
configuration. The customer has a choice to customize it for lower data rates (Gen2) or lower number of lanes. It also supports L1 sub states L1.1 and L1.2 which enables its seamless integration in power constraint applications, while keeping low in the silicon area.
T2M offers an option of complete integrated PCIe 3.0 hard IP including partner company controller and standalone PHY IP.
Available PCI PHY
PCIe 3.0 8 & 16Gbps
Foundry - 65,55,28nm
Per lane real-time, non-destructive internal
Multiple internal test patterns, including PRBS
and 256-bit user-defined pattern
Supports forward/reverse analog and digital loopbacks