The PHY IP for PCIe 3.0 is designed according to PCIe 3.0 specification. Implemented on the TSMC 16FF+LL process, the PHY IP provides a cost-effective, low-power solution. The PHY IP for PCIe 3.0 operates at 8.0GTps, 5.0GTps, and 2.5GTps. The Physical Coding Sublayer (PCS) complies with the PIPE 3.0 (v0.9) and PIPE 4.2 specification, and provides support for the dynamic equalization features of PCIe 3.0. Flexibility in board design assured due to Cadence design-in kits. The PHY IP seamlessly connects to a Cadence, or third party, PIPE 3.0-compliant or PIPE 4.2-compliant controller. The PHY IP is dedicated to applications demanding low latency and high data transfer rates.