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PCI Express Gen3 PHY in TSMC 28nm HPM
This SerDes PHY macro is designed in TSMC 28nm technology to specifically meet the PCIE GEN3 standard. This hard macro can be paired with the PCIe Controller to provide a complete PCIE solution. Test features include CMOS scan chains, JTAG boundary scan, line and serial loop back, BIST, analog test bus, and AMBA digital interface for programming. The macro will operate from 0ºC to 125ºC and is designed for a flip-chip package.
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PCIe 3 IP
- PCIe 5.0 Controller with AMBA AXI interface
- 250Mbps to 16Gbps Multiprotocol SerDes PMA
- PCIe 4.0 Controller with AMBA AXI interface
- 1G-16G SerDes IP, Supports (PCIe Gen4/3/2/1, JESD204B) (Silicon Proven in TSMC 28HPC+/HPC/HPM)
- PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 12SF+/SF++
- PCIe 4/3/2 PHY GF 22FDX