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PCI Express Gen3 PHY in TSMC 28nm HPM
This SerDes PHY macro is designed in TSMC 28nm technology to specifically meet the PCIE GEN3 standard. This hard macro can be paired with the PCIe Controller to provide a complete PCIE solution. Test features include CMOS scan chains, JTAG boundary scan, line and serial loop back, BIST, analog test bus, and AMBA digital interface for programming. The macro will operate from 0ºC to 125ºC and is designed for a flip-chip package.
Features
- BIST for manufacturing test including loopback and pattern generator, error detector, and error counter
- Automatic calibration of analog circuits and offset correction
- AMBA APB, JTAG and test mode interfaces for flexibility and ease of use
- On-chip regulation for high jitter performance
- Fully adaptive, continuous-time, linear equalizer
- Programmable 3-tap transmitter FIR with polarity inversion
Benefits
- Low-risk solution
- Extensive testability - BIST, Loop back, Scan feature with JTAG, and AMBA support
- Ease-of-use - System integration kit reduces system integration and signal integrity issues
Deliverables
- Detailed specification
- LIB timing view, LEF, GDSII
- Integration support
- Behavioral model and test benches
- Verification file LEC, DRC, LVS and ANT
Applications
- Networking
- Cloud computing
- Wireless communication equipment
- Mobile devices
- Consumer products
View PCIe 3.0 PHY IP TSMC 28HPM full description to...
- see the entire PCIe 3.0 PHY IP TSMC 28HPM datasheet
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