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PCI Express Gen3 PHY in TSMC 28nm HPM
This SerDes PHY macro is designed in TSMC 28nm technology to specifically meet the PCIE GEN3 standard. This hard macro can be paired with the PCIe Controller to provide a complete PCIE solution. Test features include CMOS scan chains, JTAG boundary scan, line and serial loop back, BIST, analog test bus, and AMBA digital interface for programming. The macro will operate from 0ºC to 125ºC and is designed for a flip-chip package.
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PCIe 3 IP
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- 250Mbps to 16Gbps Multiprotocol SerDes PMA
- PCIe 5.0 Controller IP supporting Root Complex, End Point, Switch Port compliant with PCIe 5.0/4.0/3.0/2.0/1.0 and fully synthesizable
- PCIe 3.0 Controller IP supporting Root Complex, End Point, Switch Port compliant with PCIe 3.0/2.0/1.0 and fully synthesizable
- PHY IP for PCIe 3.0 TSMC 28HPC
- Multi-Link Multi-Protocol SerDes - PHY IP for PCIe 3.0 TSMC 16FF+LL