ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 14SFP
T2M provides the best-in-class, highly configurable PCIe 3.0 PHY that complies with ECN 1.0a and PCie 3.0 specifications and is aimed at both client and corporate applications. The eight-lane arrangement of the PHY IP allows for maximum throughput while supporting a wide range of applications. It can be tailored by the client for lower data rates (Gen2) or fewer lanes. Additionally, it offers L1 substates L1.1 and L1.2, allowing for easy integration in applications with strict power requirements while maintaining minimal silicon area.
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pcie3.0ip IP
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