PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 40LP
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pcie 3.1 ip IP
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support