PCIe Gen4 Controller is a configurable and scalable for ASIC and FPGA implementation. The Controller P is compliant with the PCI Express 4.0, and 3.1/3.0 specifications, as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification. The IP can be configured to support endpoint, root port, and dual-mode topologies, allowing for a variety of use models, and exposes a configurable, flexible AMBA AXI interconnect interface to the user.
The PCIE Controller IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The PCIE Controller IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.