English
You are here:
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
With compatibility for PIPE 4.4 interface protocol, this Peripheral Component Interconnect Express (PCIe) x4 PHY complies with PCIe 4.0 Base Specification.
Support for extra PLL control, reference clock control, and inbuilt power gating control results in lower power usage. Additionally, because the previously
described low power mode option is programmable, the PHY is extensively useful for a variety of applications with diverse power consumption considerations.
Support for extra PLL control, reference clock control, and inbuilt power gating control results in lower power usage. Additionally, because the previously
described low power mode option is programmable, the PHY is extensively useful for a variety of applications with diverse power consumption considerations.
View PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP full description to...
- see the entire PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP datasheet
- get in contact with PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP Supplier
Block Diagram of the PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
PCIeIP IP
- PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 55SP
- PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
- PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
- PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 28HPC