RC digital IP controller only in verilog
EP digital controller only in verilog
Dual Mode(DM) controllers in Verilog
Hardware validation platform for RC only
Hardware validation platform for EP only
Hardware validation platform for DM only
- Compliant with PCI Express 5.0 (32
- (16 GT/s), (16 GT/s), (16 GT/s), (16 GT/s), & backward compatible. Compliant with Pipe s.x
- Supports both PIPE SERDES and non Serdes architecture
- EPI RCI DMI Switch configurations support architecture
- Compliant with ATS Specification
- Compliant with AMBA INTERFACES Latest versions
- 5 12b Controller architecture and 64B PIPE interface for very high performance
- Compliant with SR -Iov Specifications.
- Supports X 16, X8, X4, X2, I Lanes
- Highly configurable, robust DMA Highly architecture
- Flexible user interface & AXI4/Native Interfaces
- LTR, AER, OBFF, MSI, MSI LTR, AER, OBFF, ERC, and Cross link all features supported
- Required features can be turned on and off at core generation
- Phase for an optimized gate controller
- Simple Clocking architecture
- 32 Physical and 512 virtual functions supported
- Optional lnbuilt address translator Configurable
- FPGA validation @ Gen4 speed and loopback mode
- @Gen5 speed
- PCI SIG compliance test
- Digital lP controller with UVM VIP counterpart and related testbench
- components and all documentations.
- Hardware validation platforms with Full compliance testing support and error scenario support. HVPs currently available are VCU 118/ZCU 106.
- Bit file of digital IP controllers for any type of platforms.
- Standalone UVM VIP components, testcases, environment and easy to
- integrate guideline documents.
Block Diagram of the PCIe 5.0 /4.0 /3.0 Controllers IP Core