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PCIe 5.0 Controller
XpressRICH5 is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The XpressRICH5 IP is compliant with the PCI Express 5.0 rev.0.7, 4.0, 3.1, 2.1, and 1.1 specifications, as well as with the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including data path size, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power. PLDA is working hand in hand with multiple PHY IP vendors and Verification IP vendors to offer a range of integrated solutions for PCIe 5.0. PLDA XpressRICH5 PCIe IP is the #1 choice for designers requiring enterprise-class features, highest performance, reliability, and scalability.
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Block Diagram of the PCIe 5.0 Controller IP Core
Video Demo of the PCIe 5.0 Controller IP Core
In this video, we talk about the PLDA XpressRICH IP wizard which has been designed to enable PCIe designers to easily configure their PCIe controller as required for their application.
PCIe IP
- PCI Express 5.0/4.0/3.0/2.1/1.1 Core from Rambus
- PCIe 5.0 PHY in TSMC (16nm)
- Complete PCIe 4.0 Soft IP supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, AER and more
- Customizable Embedded Multi-port PCIe Switch
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- Gen5 PCIe Hybrid Controller with SR-IOV and ARI Support