XpressRICH5 is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The XpressRICH5 IP is compliant with the PCI Express 5.0 rev.0.7, 4.0, 3.1, 2.1, and 1.1 specifications, as well as with the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including data path size, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power. PLDA is working hand in hand with multiple PHY IP vendors and Verification IP vendors to offer a range of integrated solutions for PCIe 5.0. PLDA XpressRICH5 PCIe IP is the #1 choice for designers requiring enterprise-class features, highest performance, reliability, and scalability.
Complies with the PCI Express Base 5.0 Specification, Rev 0.7 and PIPE (8-, 16-, 32-, and 64-bit) specification
Supports Endpoint, Root-Port, Dual-mode, Switch Port
Supports link rate of 2.5, 5.0, 8.0, 16.0 and 32 Gbps per lane.
Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
512-bit transmit/receive low-latency user interface supporting TLP chaining (multiple packets per Tclk)
User-selectable Transaction/Application Layer Clock Frequency
Sideband signaling for PCIe configuration access, internal status monitoring, debug, interrupts, and more
Optional Transation Layer bypass
Unique Features & Capabilities
Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
Optional MSI/MSI-X register remapping to memory for reduced gate count when multi-function or SR-IOV is implemented
Smart buffer management on receive side (Rx Stream) and transmit side (merged Replay/Transmit buffer) enables lower memory footprint
Optional Transaction Layer bypass allows for customer-developed application layer
Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
20+ years of experience in design of IP cores for ASIC with specialization in high-speed interface protocols and technologies, more than 6200 customers , including several hundred of ASIC tape-outs
Allows seamless migration from FPGA prototyping design to ASIC/SoC production design with same RTL.
Availability for PCIe 5.0 early adopters
Root-port, Endpoint, Dual-mode, Switch port in depth flexible configuration
Support for advanced Low Power states enables lower power consumption in energy-conscious applications
Configurable user interface with clock-domain-crossing provides maximum interfacing flexibility and throughput.
Extensive data integrity features provide data protection on entire data path for storage and other data critical applications
Acclaimed global 24/5 support
Dedicated Advanced Design & Integration (ADI) team available to help withb development, integration, and verification
Synthesizable Verilog RTL source code
Configuration assistant GUI
PCIe Bus Functional Model simulation libraries
PCIe Linux and Windows x64 endpoint device driver (binary or source code) and C API
Reference designs for ASIC and/or FPGA implementation
XpressRICH5 is specifically engineered for ASIC, SoCs, and FPGAs designed to power demanding applications in Artificial Intelligence (AI) and Machine Learning (ML), data center storage and networking, and High Performance Computing (HPC).
Block Diagram of the PCIe 5.0 Controller IP Core
Video Demo of the PCIe 5.0 Controller IP Core
In this video, we talk about the PLDA XpressRICH IP wizard which has been designed to enable PCIe designers to easily configure their PCIe controller as required for their application.