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PCIe 5.0 Controller
XpressRICH5 is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The XpressRICH5 IP is compliant with the PCI Express 5.0 rev.0.7, 4.0, 3.1, 2.1, and 1.1 specifications, as well as with the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including data path size, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power. PLDA is working hand in hand with multiple PHY IP vendors and Verification IP vendors to offer a range of integrated solutions for PCIe 5.0. PLDA XpressRICH5 PCIe IP is the #1 choice for designers requiring enterprise-class features, highest performance, reliability, and scalability.
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Block Diagram of the PCIe 5.0 Controller IP Core
Video Demo of the PCIe 5.0 Controller IP Core
The demo showcases stable PCIe 5.0 Link Training (32 GT/s) and exceptional signal integrity with a Broadcom® PCIe 5.0 PHY platform.
This solution is based on the XpressRICH® IP Controller for PCIe 5.0 combined with Broadcom’s PCIe 5.0 PHY IP. Several different setups demonstrate that the combined IPs provide exceptional signal integrity with, robust link training at 32 GT/s and stable backward compatibility at PCIe 4.0, PCIe 3.0, PCIe 2.0 and PCIe 1.0 speeds. The results of these tests is a quality guarantee for the SoC designers who choose the combined solution of PLDA’s PCIe 5.0 Controller and Broadcom’s PHY IP.
PCIe IP
- PCI Express 5.0/4.0/3.0/2.1/1.1 Core from Rambus
- PCIe 5.0 PHY in TSMC (16nm)
- Customizable Embedded Multi-port PCIe Switch
- PCIe 5.0, 4.0, 3.1/3.0 Root Port, Endpoint, Dual-mode, Controller IP Core with Built-in Many-Channel DMA (vDMA), Legacy DMA, and Configurable AMBA AXI Interconnect
- Controller IP for PCIe 2.1 as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification
- Controller IP for PCIe 6.0, Supporting Root Port, Endpoint, Dual-mode, Switch Port Configurations with Native User Interface