PCIe 5.0 Controller IP supporting Root Complex, End Point, Switch Port compliant with PCIe 5.0/4.0/3.0/2.0/1.0 and fully synthesizable

The Peripheral Component Interconnect Express Controller IP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The PCIE Controller IP can be implemented in any technology. The PCIE Controller IP core supports the PCI 5.0 Specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture – AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol. The PCIE Controller IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The PCIE Controller IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.

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