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PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
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Block Diagram of the PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection

PCIe 5.0 IP
- PCIe 5.0 PHY in TSMC (16nm)
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- Configurable controllers for PCIe 5.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications