Dual thread, superscalar, embedded 32-bit RISC-V core with 9-stage pipeline
PCIe 5.0 PHY IP with 32GT/s optimized for low power consumption (Silicon Proven in TSMC 12FFC)
The PHY meets the needs of today’s high-speed chipto-chip, board-to-board, and backplane interfaces while being extremely low in power and area.
Verification
PCIe PHY functionality is verified in NCVerilog simulation software using test bench written in Verilog HDL
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Block Diagram of the PCIe 5.0 PHY IP with 32GT/s optimized for low power consumption (Silicon Proven in TSMC 12FFC)
PCIeIP IP
- PCIe 5.0 Controller IP supporting Root Complex, End Point, Switch Port compliant with PCIe 5.0/4.0/3.0/2.0/1.0 and fully synthesizable
- PCIe 3.0 PHY IP with 8GT/s optimized for low power consumption (Silicon Proven in TSMC 28HPC+)
- PCIe 4.0 PHY IP with 16GT/s optimized for low power consumption (Silicon Proven in TSMC 28HPC+)
- PCIe 2.0 PHY IP with 5GT/s (Silicon Proven in TSMC 28HPC+)
- Quad Lane 5Gbps PCIe 2.0 PHY IP (Silicon Proven in TSMC 22ULP/ULL)
- PCIe Gen2 PHY IP (Silicon Proven in SMIC 40LL)