PCIe 5.0 SerDes PHY
How PCIe 5.0 Works
The Rambus PCIe 5.0 PHY with the Rambus PCIe 5.0 digital controller comprise a high-performance serial link subsystem. Optimized for power in challenging, high-loss channels, our PCIe 5.0 interface solution is ideal for performance-intensive AI, data center, edge, 5G infrastructure and graphics applications.
The PHY consists of a PMA hard macro that supports PCIe 5.0, 4.0, 3.0 and 2.0 protocols and a physical coding sublayer (PCS) soft macro for PCIe that is PIPE 5.2 compliant. Co-verified with the PCIe 5.0 digital controller, the PHY can also be integrated with 3rd-party PIPE 5.2-compliant controllers.
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Block Diagram of the PCIe 5.0 SerDes PHY IP Core

PCIe 5.0 SerDes PHY IP
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
- PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 55SP
- 32G Medium Reach Multi-Protocol SerDes PHY
- PCIe 5.0 PHY