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PCIe 5.0 SerDes PHY
The Rambus PCI Express (PCIe) 5.0 and Compute Express Link (CXL) PHY is a low-power, area-optimized, silicon IP core designed with a system-oriented approach to maximize flexibility and ease of integration. It delivers up to 32 GT/s data rates in performance-intensive applications for artificial intelligence (AI), data center, edge, 5G infrastructure and graphics. With the Northwest Logic Expresso 5.0 controller core it comprises a complete PCIe 5.0 SerDes subsystem. Alternatively, it can be integrated with PIPE 5.2-compliant 3rd-party controllers. The PCIe 5 SerDes PHY supports PCIe 5.0, 4.0, 3.0 and 2.0, and has full support for manufacturability.
How PCIe 5.0 Works
The Rambus PCIe 5.0 PHY with the Expresso 5.0 digital controller comprise a high-performance serial link subsystem. Optimized for power in challenging, high-loss channels, our PCIe 5.0 interface solution is ideal for performance-intensive AI, data center, edge, 5G infrastructure and graphics applications.
The PHY consists of a PMA hard macro that supports PCIe 5.0, 4.0, 3.0 and 2.0 protocols and a physical coding sublayer (PCS) soft macro for PCIe that is PIPE 5.2 compliant. Co-verified with the Northwest Logic Expresso 5.0 digital controller, the PHY can also be integrated with 3rd-party PIPE 5.2-compliant controllers.
How PCIe 5.0 Works
The Rambus PCIe 5.0 PHY with the Expresso 5.0 digital controller comprise a high-performance serial link subsystem. Optimized for power in challenging, high-loss channels, our PCIe 5.0 interface solution is ideal for performance-intensive AI, data center, edge, 5G infrastructure and graphics applications.
The PHY consists of a PMA hard macro that supports PCIe 5.0, 4.0, 3.0 and 2.0 protocols and a physical coding sublayer (PCS) soft macro for PCIe that is PIPE 5.2 compliant. Co-verified with the Northwest Logic Expresso 5.0 digital controller, the PHY can also be integrated with 3rd-party PIPE 5.2-compliant controllers.
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Block Diagram of the PCIe 5.0 SerDes PHY IP Core
PCIe 5.0 SerDes PHY IP
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 5.0 PHY IP with 32GT/s optimized for low power consumption (Silicon Proven in TSMC 12FFC)
- PCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP
- PCI Express 5.0/4.0/3.0/2.1/1.1 Core from Rambus
- PCIe 3.0 PHY IP with 8GT/s optimized for low power consumption (Silicon Proven in TSMC 28HPC+)
- PCIe 4.0 PHY IP with 16GT/s optimized for low power consumption (Silicon Proven in TSMC 12FFC)