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90nm OTP Non Volatile Memory for Standard CMOS Logic Process
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PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
For high-bandwidth applications, the PCIe 5.0 PHY IP offers excellent performance, multi-lane capabilities, and low power design. The PCIe 5.0 IP complies with the PIPE 5.2 standard and supports the whole spectrum of PCIe 5.0 Base applications. High-speed mixed-signal circuits are included into the IP to accommodate 32Gbps PCIe 5.0 traffic.
The PCIe4.0 data rate at 16 Gbps, the PCIe 3.1 data rate at 8.0 Gbps, the PCIe 2.1 data rate at 5.0 Gbps, and the PCIe data rate at 2.5 Gbps are all backward compatible with this device. The needs for various channel conditions may be met by the PCIe 5.0 IP thanks to its support for both TX and RX equalization methods.
The PCIe4.0 data rate at 16 Gbps, the PCIe 3.1 data rate at 8.0 Gbps, the PCIe 2.1 data rate at 5.0 Gbps, and the PCIe data rate at 2.5 Gbps are all backward compatible with this device. The needs for various channel conditions may be met by the PCIe 5.0 IP thanks to its support for both TX and RX equalization methods.
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Block Diagram of the PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
PCIe IP core IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- PCIe 6.0 Integrity and Data Encryption Security Module
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Multi-protocol SerDes PMA
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP