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PCIe 6.0 Controller supporting Root Port, Endpoint, Dual-mode, Switch Port Configurations with native user interface
The PLDA PCI Express (PCIe) 6.0 Controller (formerly XpressRICH) is configurable and scalable controller IP designed for ASIC implementation. The controller supports the PCIe 6.0 specification, including 64 GT/s data rates, PAM4 signaling, FLIT mode, and L0p power state. The PCIe 6.0 architecture will be essential for SoC designers creating next-generation chips that require the movement of large amounts of data within systems, including applications like HPC, cloud computing, artificial intelligence/machine learning (AI/ML), enterprise storage, networking, and automotive.
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Block Diagram of the PCIe 6.0 Controller supporting Root Port, Endpoint, Dual-mode, Switch Port Configurations with native user interface
PCIe 6.0 IP
- PHY for PCIe 6.0 and CXL for TSMC 5nm FinFet
- PCIe 6.0 PHY G2 , TSMC N5 x4, North/South (vertical) poly orientation
- PCIe 6.0 Premium Controller
- PCIe 6.0 Controller IP with AMBA bridge
- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI Interfaces
- DesignWare® Integrity and Data Encryption (IDE) Security IP Module for PCIe 6.0