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PCIe 6.0 PHY G2 , TSMC N5 x4, North/South (vertical) poly orientation
The multi-channel DesignWare PHY IP for PCI Express (PCIe) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interface card (NIC), backplane, and chip-to-chip interfaces. The PHY’s unique DSP algorithms optimize analog and digital equalization and the patent pending diagnostics features enable near zero link downtime. The PHY minimizes package crosstalk, allows dense SoC integration for x16 links, and achieves ultra-low-latency with an optimized data path that is based on an ADC architecture. Support for multiple standards form factors including OCP 3.0, U.2, and U.3 enables server and storage applications.
The DesignWare PHY IP for PCIe 6.0 seamlessly interoperates with DesignWare Controller IP for PCIe 6.0 to provide a low-risk solution that designers can use to accelerate time-to-market and efficiently deliver differentiated products that require the 64GT/s PCIe 6.0 technology.
The DesignWare PHY IP for PCIe 6.0 seamlessly interoperates with DesignWare Controller IP for PCIe 6.0 to provide a low-risk solution that designers can use to accelerate time-to-market and efficiently deliver differentiated products that require the 64GT/s PCIe 6.0 technology.
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Video Demo of the PCIe 6.0 PHY G2 , TSMC N5 x4, North/South (vertical) poly orientation
This PCI-SIG DevCon 2022 video shows the industry’s first complete hardware demo of PCIe 6.0 with an end-to-end system from root complex to endpoint. The demo uses the Synopsys PCIe 6.0 Controller and PHY IP and shows successful link up and performance metrics.
PCIe IP
- PCIe Controller Testbench
- PCIe 5.0 PHY in TSMC (16nm)
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features