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PCIe 6.0 SerDes PHY
The Rambus PCI Express® (PCIe®) 6.0 PHY is a low-power, area-optimized, silicon IP core designed with a system-oriented approach to maximize flexibility and ease of integration. It delivers up to 64 GT/s signaling rates in performance-intensive applications for artificial intelligence (AI), data center, edge, networking, and HPC.
The PCIe 6.0 PHY can be combined with the Rambus PCIe 6.0 controller core to make a complete PCIe 6.0 interface subsystem.
How the PCIe 6.0 Interface Works
The Rambus 6.0 PHY IP consists of a Physical Media Attachment (PMA) designed with a minimal set of broadside controls and status pins, as well as a configurable Physical Coding Sublayer (PCS), to support a wide range of server, storage and networking applications. The PHY can be combined with the Rambus PCIe 6.0 digital controller to offer a fully integrated and validated interface subsystem.
The PHY is configurable in x1, x2, x4, x8 and x16 lane configurations with bifurcation support. This gives the PHY improved flexibility and support for a wide range of applications. Multi-tap transmitter and adaptive receiver equalization supports more than 36dB of channel insertion loss. The PHY also supports the latest version of the Compute Express Link™ (CXL™) specification, version 3.0, enabling new use models for data center architectures.
The PCIe 6 SerDes PHY is available on advanced process nodes.
The PCIe 6.0 PHY can be combined with the Rambus PCIe 6.0 controller core to make a complete PCIe 6.0 interface subsystem.
How the PCIe 6.0 Interface Works
The Rambus 6.0 PHY IP consists of a Physical Media Attachment (PMA) designed with a minimal set of broadside controls and status pins, as well as a configurable Physical Coding Sublayer (PCS), to support a wide range of server, storage and networking applications. The PHY can be combined with the Rambus PCIe 6.0 digital controller to offer a fully integrated and validated interface subsystem.
The PHY is configurable in x1, x2, x4, x8 and x16 lane configurations with bifurcation support. This gives the PHY improved flexibility and support for a wide range of applications. Multi-tap transmitter and adaptive receiver equalization supports more than 36dB of channel insertion loss. The PHY also supports the latest version of the Compute Express Link™ (CXL™) specification, version 3.0, enabling new use models for data center architectures.
The PCIe 6 SerDes PHY is available on advanced process nodes.
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Block Diagram of the PCIe 6.0 SerDes PHY IP Core
