PCIe DMA Controller (Low Latency)

Features

• Implements standard Transaction layer functions e.g. TLP generation/reception, TLP completion handling and interrupt generation
• Implements 32-bit, 64-bit, 128-bit and 256-bit User application. (Width selection is based on PCIe endpoint interface width)
• PCIe Gen1, Gen2 and Gen3 support.
• Up to 8 independent DMA channels with each channel capable of operating in Block-DMA or Scatter-Gather DMA modes
• Each channel capable of operating on a separate clock-domain at the user application interface
• High Performance core with minimum latency and lowest inter transaction gaps
• Credits based transfer allows efficient use of available bandwidth
• 32-bit and 64-bit systems address support with ability to dynamically switch the modes based on most significant 32-bit address field
• Supports transaction reordering for completion TLPs
• Highly parameterized design that supports multiple end point Interfaces, Data widths and number of channels
• Multiple Read Request size and Maximum payload size support
• Internal Completion timeout counters implemented
• Support for MSI and Legacy Interrupts
• Per channel DMA Interrupt Enable/Disable support.
• Support for 1-byte to 4GB of DMA transfers

Benefits

• Low Latency
• Low logic utilzation

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