Atria Logic Pvt. Ltd. provides the complete design services for PCI Express. (2.5GT/s, 5GT/s) Our expertise overs the breadth of PCI-SIG’s 3.0 specification of PCIe. We have a highly skilled team of experts who can deliver the services on PCIe physical layer including
PIPE interface (8 bit, 16 bit and 32 bit interface)
The PHY layer is essentially the PIPE (Physical Interface for PCIe Express). The designed PIPE interface follows the INTEL’s PIPE spec. This Intel's spec is being used by other vendors like Xilinx, Altera and PLDA with slight modifications in LTSSM and power management states. However the basic Interface mentioned in Intel's spec is maintained by all vendors and so our design.
The main goal of Physical Layer is to establish the physical connection or channel for proper communication of transactions coming from above layer (Transaction Layer and Data Link Layer).
The main functions of Tx side of PHY layer are listed below
Link training through ordered sets TS1 & TS2
Insertion of SKP ordered sets every 1538 symbols for elastic buffer overflow/underflow management.
Sending Logical Idles in particular state of LTSSM and whenever there is no data available to send.
Sending ElOS (Electrical Idle) as dictated by ASPM and Software Power management.
Sending FTS(Fast Training Sequence) ordered sets whiling coming back to active state from Low power state.
Generation of PIPE signals which includes
Tx_data[32 or 16 bit]
D/K [4 or 2bit]
Insertion of STP, SDP, END kontrol characters (Implemented in DLL)
All the Data packets except Kontrol characters and ordered sets will pass through scrambler.
- Fully compliant with PCI-SIG’s PCIe v2.0 specification.
- PHY package includes configurable PIPE interface (8 bit/ 16 bit/ 32bit). User can choose the interface width as per the application requirement.
- Generates whole range of Ordered Sets as required by PCIe 2.0 Specification with synchronized LTSSM.
- IBM implementation compatible 8b/10b Encoder and Decoder.
- Proprietary PCIe Scrambler that supports 8/16/32 bit interfaces.
- Highly efficient architecture with minimal gate count.
- Minimal latency and high throughput.
- Perfect recovery of data at receiver as per PCIe v2.0 Specification with packet filter that recognizes all Ordered Sets.
- Intel PIPE Interface specification v2.0 compatible implementation.
- Built-in COM Detection circuit.
- PCIe compatible proprietary elastic buffer.
Block Diagram of the PCIe Gen1/2 PHY IP Core