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PCIe Gen2 PHY
* Endpoint or Root Complex
* PIPE includes skip insertion, deletion
* PCIe power savings modes
* Port bifurcation support
* PIPE includes skip insertion, deletion
* PCIe power savings modes
* Port bifurcation support
View PCIe Gen2 PHY full description to...
- see the entire PCIe Gen2 PHY datasheet
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Block Diagram of the PCIe Gen2 PHY IP Core
SerDes IP
- 250Mbps to 12.7Gbps Multiprotocol SerDes PMA
- 250Mbps to 16Gbps Multiprotocol SerDes PMA
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP
- 32G Multi Rate SerDes PHY - GlobalFoundries 22FDX