PCIe Gen2 PHY

Features

• PCI Express Gen 2 and Gen 1 compliant
• Supports various PCI Express modes and extensions
• Programmable amplitude and pre-emphasis
• Programmable receiver equalization
• PIPE v2.0 compliant signals
• Three different build configurations are supported for customer applications
• Status pins for checking PHY functionality
• Integrated bandgap
• Automatic driver/receiver impedance calibration

Benefits

• Low Risk - Silicon proven today in multiple foundries and processes with Extensive Si characterization data
• Excellent Interoperability - LC tank oscillator that gives low noise and jitter
• Superior Noise Immunity - Fully differential circuitry and Voltage Regulator for enhanced noise immunity
• Low Power - As low as 60mW per lane at 3.125Gb/s
• Minimal Area - for Wire bond as well as flip-chip package
• Improve Test Coverage - Multiple loopback modes with 12 built-in patterns
• Scan built in to all digital,Serial Control Register (SCR) for simplified testing, JTAG support (DC and AC )
• Lowest Total Cost of Ownership
• Customization/ Integration support

Deliverables

• Abstract LEF
• Behavioral Model Verilog
• Timing Model .lib
• High-speed IO Model hSpice
• LVS Netlist cdl
• Physical database GDSII
• Documentation pdf
• PIPE Interface rtl

Applications

• Consumer
• Server
• Industrial

Block Diagram of the PCIe Gen2 PHY IP Core

• see the entire PCIe Gen2 PHY datasheet
• get in contact with PCIe Gen2 PHY Supplier