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PCIe Gen3 PHY - TSMC 28nm HPC/HPC+
* Endpoint or Root Complex
* PCIe standard multi-lane interface
* PCIe power savings modes
* Port bifurcation support
* PCIe standard multi-lane interface
* PCIe power savings modes
* Port bifurcation support
View PCIe Gen3 PHY full description to...
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Block Diagram of the PCIe Gen3 PHY - TSMC 28nm HPC/HPC+
SerDes IP
- Low Power Multiprotocol SerDes PMA
- 250Mbps to 12.7Gbps Multiprotocol SerDes PMA
- 125Mbps to 16Gbps Multi-protocol SerDes PMA
- 250Mbps to 8.1Gbps Multi-protocol SerDes PMA, wire-bond
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency